With the advance of technology in integrated circuits (ICs), the minimum feature sizes of ICs have been shrinking for years. Commensurate with this size reduction, various process limitations have made IC fabrication more difficult. One area of fabrication technology in which such limitations have appeared is photolithography. Photolithography involves selectively exposing regions of a resist coated silicon wafer to a radiation pattern, and then developing the exposed resist in order to selectively protect regions of wafer layers (e.g., regions of substrate, polysilicon, or dielectric).
An integral component of a photolithographic apparatus is a “mask” or “reticle” which includes a pattern corresponding to features at one layer in an IC design. Such reticle may typically include a transparent glass plate covered with a patterned light blocking material such as chromium. The reticle may be placed between a radiation source producing radiation of a pre-selected wavelength and a focusing lens which may form part of a “stepper” apparatus. Placed beneath the stepper may be a resist covered silicon wafer. When the radiation from the radiation source is directed onto the reticle, light may pass through the glass (regions not having chromium patterns) and project onto the resist covered silicon wafer. In this manner, an image of the reticle may be transferred to the resist. The resist (sometimes referred to as a “photoresist”) is provided as a thin layer of radiation-sensitive material that is spin-coated over the entire silicon wafer surface.
As light passes through the reticle, the light may be refracted and scattered by the chromium edges. This may cause the projected image to exhibit some rounding and other optical distortion. While such effects pose relatively little difficulty in layouts with large feature sizes (e.g., layouts with critical dimensions above about 1 micron), the effects may not be ignored in layouts having features smaller than about 1 micron. The problems become especially pronounced in IC designs having feature sizes near the wavelength of light used in the photolithographic process. Optical distortions commonly encountered in photolithography may include rounded corners, reduced feature widths, fusion of dense features, shifting of line segment positions, and the like. Unfortunately, any distorted illumination pattern may propagate to a developed resist pattern and ultimately to IC features such as polysilicon gate regions, vias in dielectrics, and the like. As a result, the IC performance may be degraded or the IC may become unusable.
To remedy this problem, a reticle correction technique known as optical proximity correction (“OPC”) has been developed. Optical proximity correction may involve adding regions to and/or subtracting regions from a reticle design at locations chosen to overcome the distorting effects of diffraction and scattering. Typically, OPC is performed on a digital representation of a desired IC pattern. First, the digital pattern may be evaluated with software to identify regions where optical distortion will result. Then the optical proximity correction may be applied to compensate for the distortion. The resulting pattern may be ultimately transferred to the reticle glass. OPC may add various “corrections” to base features. For example, some correction may take the form of “serifs,” which are small appendage-type addition or subtraction regions typically made at corner regions on reticle designs. These “serifs” may have the intended effect of “sharpening” the corners of the illumination pattern on the wafer surface.
With OPC, the boundary of an IC design often needs to be moved and/or distorted. In order to get a better correction, it is often useful to introduce more vertices on the boundary to give the IC designer more freedom to design the IC. However, as the number of the vertices grows, the complexity of the masks (thus the cost) may grow. In addition, during the OPC process the fragment of the boundary edge often moves at an essential distance from its initial position, resulting in more complex structure with higher density than the initial design. This may cause different process intensity.
Therefore, it would be desirable to provide a method and apparatus for optimizing fragmentation of boundaries for OPC purposes, which may balance the number of vertices and the “flexibility” of the boundary and may recover fragmentation according to the process intensity profile along the ideal edge position to obtain the best decision for OPC.